Many computer applications (e.g., image processing, graphics rendering, video processing, etc.) require the manipulation of large data arrays (e.g., frame buffers). Such applications benefit greatly from tiling, a technique in which the data arrays are partitioned and mapped to memory by software, hardware, or a combination thereof. Algorithms that manipulate the tiled data arrays often have dramatically reduced paging activity and execution times in such tiled virtual memory systems.
Some digital systems include specialized memory management hardware and operating system support for managing a tiled virtual memory that is shared by the applications. One such system is described in Franklin, James, “Tiled Virtual Memory for Unix,” USENIX, June, 1992, pp. 99-106. In many such systems, a portion of physical memory is reserved for use as tile memory and tiled virtual memory management is implemented. Special memory mapping logic is present to translate array (i.e., two-dimensional) virtual addresses into tiled virtual memory addresses and ultimately into physical memory addresses. While the specialized software and hardware support improves performance of the applications that manipulate large data arrays, improvements in physical memory allocation and reduced complexity in managing the tiled virtual memory space are desired to further improve performance.